CEA-Leti and Stanford Target Edge-AI Apps with Breakthrough NVM Memory Cell

CEA-Leti and Stanford Target Edge-AI Apps with Breakthrough NVM Memory Cell

Researchers at CEA-Leti and Stanford have developed the world’s 1st circuit integration multiple-bit non-volatile memory (NVM) technology known as Resistive RAM (RRAM) with atomic number 14 computing units, in addition as new memory resiliency options that give a pair of.3-times the capability of existing RRAM. Target applications embody energy-efficient, smart-sensor nodes to support computer science on the net of Things, or “edge AI”.

The proof-of-concept chip has been valid for a good style of applications (machine learning, control, security). Designed by a Stanford team LED by Professors Subhasish Hindu deity and H.-S. prince Wong and accomplished in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates 2 heterogeneous technologies: eighteen kilobytes (KB) of on-chip RRAM on prime of economic 130nm atomic number 14 CMOS with a 16-bit all-purpose microcontroller core with 8KB of SRAM.

The new chip delivers 10-times higher energy potency (at similar speed) versus customary embedded FLASH, due to its low operation energy, in addition as ultra-fast and energy-efficient transitions from on mode to off mode and the other way around. to save lots of energy, smart-sensor nodes should flip themselves off. Non-volatility, that allows recollections to retain knowledge once power is off, is therefore changing into a necessary on-chip memory characteristic for edge nodes. the look of two.3 bits/cell RRAM allows higher memory density (NVM dense integration) yielding higher application results: a pair of.3x higher neural network reasoning accuracy, for instance, compared to a 1-bit/cell equivalent memory.

The technology was given on February. 19, at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco during a paper titled, “A four3pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up integration a pair of.3-bit/Cell Resistive RAM and Resilience Techniques”.

But NVM technologies (RRAM and others) suffer from write failures. Such write failures have harmful impact at the applying level and considerably diminish the quality of NVM like RRAM. The CEA-Leti and Stanford team created a replacement technique known as ENDURER that overcomes this major challenge. this provides the chip a 10-year purposeful life once incessantly running reasoning with the changed National Institute of Standards and Technology (MNIST) information, for instance.

Source: scienceandtechnologyresearchnews.com